With the rapid development of semiconductor manufacturing technologies, the semiconductor devices have been developed toward high device density and high integration level. As the basic semiconductor devices, transistors have been widely used. With the continuous increase of the device density and the integration level of the semiconductor devices, the size of the transistors has become smaller and smaller.
A transistor often includes a semiconductor substrate; a gate structure on the semiconductor substrate; sidewall spacers on the sidewall surfaces of the gate structure; and a doped source/drain layer in the semiconductor substrate at both sides of the gate structure. To increase the carrier mobility of the channel region of the transistor, the strained silicon technology has been introduced in the fabrication of semiconductor devices. The strained silicon technology causes the crystal lattice of the doped source/drain layer to be different from the crystal lattice of the semiconductor substrate so as to cause the doped source/drain layer to generate a stress to the channel region. Accordingly, the carrier mobility of the channel region is increased. At the same time, the gate structure, the sidewall spacers and the doped source/drain layer form capacitors. The capacitors have parasitic capacitances.
However, the semiconductor structure may be unable to match the requirements of a small parasitic capacitance and a large carrier mobility simultaneously. The disclosed methods and semiconductor structures are directed to solve one or more problems set forth above and other problems in the art.